1. Field of Invention
The present invention relates to a method for manufacturing ultra large-scale integrated (ULSI) circuits. More particularly, the present invention relates to a method for patterning interconnects on a semiconductor wafer using a dual damascene process.
2. Description of Related Art
The dual damascene process, in which metal is skillfully buried inside patterned grooves in a substrate, is frequently used these days and has become one of the best methods for fabricating integrated circuits. Conventionally, metallic interconnects are formed by depositing a metallic layer over an insulating layer, for example, a silicon dioxide layer. Then, the insulating layer is etched to form a pattern of predefined conductive lines so that a vertical contact window can be formed between conductive layers. Thereafter, metallic material similar or dissimilar to the conductive layer is deposited into the contact window to complete vertical connection between the conductive layers.
FIG. 1 is a cross-sectional view showing a metallic interconnect above a semiconductor substrate fabricated according to a conventional method. As shown in FIG. 1, the method of fabrication includes providing a substrate 10, and then patterning a device area 11. Thereafter, a first insulating layer 12 is formed above the substrate 10 followed by patterning. Next, a first metallic layer 13 is deposited over the substrate 10 so that the first metallic layer 13 is electrically coupled to the device area 11 through a contact window 14. Similarly, a second insulating layer 15 is formed over the first metallic layer 13. Then, a second metallic layer 16 is formed over the second insulating layer 15 so that the second metallic layer 16 is electrically connected to the first metallic layer 13 through a contact window 17. Finally, a third insulating layer 19 is formed over the device to protect the structure.
A slant angle is made on the sidewalls of the contact window when the dialectric windows are etched to form contact windows 14 and 17. The slant angle ensures good continuity of the metallic layer when using the method discussed above. However, if the slant angle is too steep, the metal at the corner edges of the contact window can be damaged quite easily. On the other hand, if the slant angle is too gentle, although continuity in a metallic conductive line is greatly improved, wafer area occupation tends to increase so that compact window structures are difficult to achieve. Moreover, the dielectric windows and contact windows will create a rather uneven surface such that subsequent interconnect layer fabrication becomes very difficult. Although FIG. 1 is not drawn according to scale, it is obvious that the uneven upper surface can easily lead to reliability problems. One problem that can happen at the interface location S between the first metallic layer and the second metallic layer is short-circuiting. This is because the insulating layer in the neighborhood of S is too thin. Another problem that can happen is an open-circuit condition due to the formation of a thin metallic layer near O.
A dual damascene method of fabrication is now commonly used to resolve the above problems. FIGS. 2A through 2D are cross-sectional views showing the progression of manufacturing steps in producing a dual damascene interconnect structure in a semiconductor substrate according to a conventional dual damascene method. First, as shown in FIG. 2A, a substrate 30 is provided. On this substrate 30, patterned metallic layers 31 are already formed. Next, a dielectric layer 32 is formed above the substrate 30, and then the dielectric layer 32 is planarized so that its thickness is same as the vertical height of a subsequently formed plug. Thereafter, dielectric layer 33 and dielectric layer 34 are sequentially formed above the dielectric layer 32. In the subsequent step, using conventional photolithographic and etching methods, the dielectric layers 32, 33 and 34 are patterned to form a vertical window 36 exposing a metallic layer 31 on the substrate 30. Later, a photoresist layer 38 is formed over the substrate 30. Then, using a fixed dose of light 40, patterns on a photomask 41 are transferred to the photoresist layer 38.
Next, as shown in FIG. 2B, the photoresist layer 38 is developed. Hence, a horizontal trench pattern 42 is formed exposing the vertical window 36 and the metallic layer 31 below.
Subsequently, as shown in FIG. 2C, using the photoresist layer 38 as a mask and the dielectric layer 33 as an etching stop layer, an etching operation is performed. For example, an anisotropic etching process is used such that the horizontal trench pattern 42 is transferred down to the dielectric layer 34 to form a horizontal trench 42'.
Finally, as shown in FIG. 2D, the photoresist layer 38 is removed, and metallic material 44 is deposited into the vertical window 36 and the horizontal trench 42'. Subsequently, extra metallic material 44 deposited above the dielectric layer 34 is removed using a chemical-mechanical polishing (CMP) method to complete the fabrication of a dual damascene metallic structure.
The above dual damascene process is able to reduce problems caused by windows and metallic conductive lines, and will improve the tolerance of over-coverage problems. Furthermore, even at the lowest allowed errors of design rules, the integrity of the conductive lines can still be maintained. In addition, it can avoid all the problems caused by depositing a thin layer of insulating material or metal over a window having slanting sides. However, there is still the problem that the metallic layer 31 at the bottom of the vertical window 36 is exposed and unprotected, and so will be etched by the etchant in the process of forming the horizontal trench 42. Consequently, the metallic layer 31 can be easily damaged resulting in a change in device properties, and ultimately may have to be scrapped.
In light of the foregoing, there is a need to provide an improved method of forming dual damascene structures.